The present invention relates to a method of manufacturing a system large-scale integration (LSI) with a core processor, a memory and a peripheral circuit mounted on a single chip and a system LSI manufactured using the particular method, and, in particular, to a method of manufacturing a flexible system LSI chip (FlexSys) which can reduce both the cost and the power consumption, of the system LSI, at the same time.
With the recent progress of micromachining techniques, a system LSI with a system mounted on a single chip has become possible. The system LSI is configured with hardware and software. In the description that follows, it is assumed that the hardware includes a processor, a data memory, an instruction memory and a peripheral circuit, and the software includes an application program.
For reducing the manufacturing cost of the system LSI, reusability must be improved for both hardware and software. The overhead per chip can be reduced by sharing the process of design and manufacture and increasing the substantial production quantity in each process by the reuse of hardware and software.
In designing a embedded system, a processor-based system design is widely employed. This design, including a processor, has two advantages. One is that the specification can be easily changed even in the final stage of the design process. The second advantage is that the design change can be easily accomplished. In the processor-based system design, the reuse of hardware and software greatly contributes to the cost reduction of the system design.
In the processor-based embedded system design, most of the system functions are realized by software. The functions required of the system are becoming more complicated year by year and therefore the software cost increases. Further, with the shortening of the product life and variation of products, an increasingly heavier load is being imposed on software developers. To reduce the software development cost, many software developers convert the functions to parts and reuse the parts. As one example, a program for realizing widely-used functions such as OS and communication control is reused.
For the system LSI with the system functions integrated on a single chip, on the other hand, the design reuse of hardware as well as software is an indispensable technique. The reuse of hardware can reduce the unit cost of the chip. This is by reason of the fact that the reuse makes possible the mass production and reduces the design cost per unit chip and the mask production cost. An example of hardware reuse intended to reduce the chip unit cost by mass production of devices having different purposes is the reuse of base wafers such as gate arrays and FPGAs (field programmable gate arrays). In these approaches, LSIs of a given type having freedom of design at a transistor or gate level are produced in a great quantity, and their purposes are determined in a stage near to the final process thereby to realize a reduced price of the chip. The introduction of this approach to the system LSI with a processor, a memory and an input/output circuit integrated on a single chip is, however, difficult because of the performance and power overhead.
In view of this, the reuse of hardware widely used now for the embedded system is the reuse of the processor and the memory cores.
The embedded software is increasing in size and it is complicated, and it is necessary to improve the reusability in more versatile ways, for all the architectures. Nevertheless, it is considered difficult to reduce both the cost and the power consumption of the system LSI at the same time. The reason is as follows. Now that the restrictions on the heat generation and the battery life are becoming more and more strict, the system LSI is desirably specialized as far as possible for respective applications. The specialization of the system LSI, on the other hand, reduces the possibility of reuse. Further, in view of the trend toward a shorter product life, the production volume of the system LSI is limited. This increases the chip unit cost. A technique is required, therefore, to allow design of the system LSI for general-purpose applications, as far as possible, to permit reuse.
Japanese Unexamined Patent Publication No. 58-186824, for example, proposes a method in which contacts are formed in a required pattern to cut off power supply to those function blocks, integrated on a single semiconductor chip, which are not used for executing the application program. In the actual system LSI, however, there is substantially no block which is not used at all. Namely, a part of every block operates. The proposed method, therefore, fails to exhibit a sufficient effect.
The reuse of the hardware and software of the system LSI will be discussed in more detail. In the following description, the effect that design reuse has on the chip unit cost will be studied using the chip unit cost of LSI as a model.
Let D be the design cost of the LSI, M be the mask production cost, N the number of LSIs with no fault, and F be the production cost per chip (approximated by the chip area). The unit cost P of the LSI is approximated by equation (1).
P=(D+M)/N+Fxe2x80x83xe2x80x83(1)
Equation (1) shows that with the increase in N, i.e. by manufacturing the same LSI in a large volume, the design cost per chip and the mask production cost are reduced. The micro controller is an example. The micro controller, which is designed as a general-purpose device intended for a plurality of applications, is reusable and the chip thereof is low in cost.
Improving the design reusability makes possible mass production of the chips and can reduce the unit cost thereof. Now, the effect that the design reuse has on the chip unit cost will be analyzed. Assume that a total of N system LSIs are designed for k different applications. The chip unit cost will be compared between two designs (a) and (b). In design (a), one system LSI is commonly used for k applications, while in design (b) k system LSIs are designed. Let Pxe2x80x2 be the unit cost of the chip designed by the method (a), and Pi be the unit cost of the chip designed by the method (b). Both can be approximated by equations (2) and (3) below.
Pxe2x80x2=(Dxe2x80x2+Mxe2x80x2)/N+Fxe2x80x2xe2x80x83xe2x80x83(2)
Pi=(Di+Mi)/ni+Fixe2x80x83xe2x80x83(3)
The relation between N and ni is expressed by equation (4) below.                                           ∑                          i              =              0                        k                    ⁢                      xe2x80x83                    ⁢          ni                =        N                            (        4        )            
Assuming that Dxe2x80x2≈Di and Mxe2x80x2≈Mi, the figure for the case using a single LSI, i.e. the first term of equation (2) above is much smaller. The manufacturing cost F (Fxe2x80x2, Fi) of the second term, on the other hand, is strongly related to the yield rate determined by the chip area. Generally, the specialization reduces the chip area, and therefore the relation Fxe2x80x2 greater than Fi holds. In other words, specialization is recommended for reducing the second term.
As one of the methods for solving the above-mentioned problems, a technique of limiting the range of reuse and using a single LSI for a plurality of applications, i.e. a technique of designing one type of LSI for k (k greater than 1) applications is widely used. A small-scale system built into domestic electric appliances and mainly in charge of the control operation thereof, for example, uses a small-scale LSI such as a 4-bit microcomputer, while a portable information terminal involving sophisticated signal processing therein uses a large LSI such as a 32-bit microcomputer.
The current general-purpose microcomputers, however, have the power consumption and the basic performance thereof fixed by the chip and are not easily used for different applications in a versatile way without packaging more than the required circuits or the wasteful use of the silicon area. The range of reuse is limited, and therefore a 4-bit system is not realized in a 32-bit microcomputer, for example. Nevertheless, the problem is posed that unrequired power consumption occurs in each range. In the case where a 32-bit microcomputer is used for applications to process not more than 24-bit data, for example, the memory mounted in the microcomputer has an area beyond the variables requiring only the accuracy of 24 bits and therefore includes an area completely unused. In such a case, not a small amount of power is consumed by the unrequired upper bits of datapath.
As described above, reusing a system LSI for various applications as far as possible, though one method of reducing the chip unit cost, is accompanied by the problem of an increased unrequired power consumption. The unrequited power consumption is derived from the unrequired switching operation of parts of the function unit, register and bus of the processor. In the case where 8-bit coded characters are processed on a 32-bit processor, for example, the most significant 24 bits in the data bus and the processor have no meaning. A switching operation in this unused area leads to the waste of power.
In similar fashion, unrequired power may be consumed by the memory. In the case where the processor reads a variable x having the size of 32 bits from memory, for example, the precharge circuit of the memory, the sense amplifier circuit, the bit line and the word line are driven to consume power. When the maximum value of the variable x is 1 and the minimum value thereof is 0 for all input data (in the case where x is used as a flag, for example), the power consumed for reading the data of the most significant 31 bits from the memory is wasteful. It is also clear from the foregoing description that the unrequired power consumption may be caused by the bus between the memory and the processor.
In a large-scale circuit such as the system LSI, the unrequited parts of the circuit have a large effect on the chip unit cost. The power consumed by the unrequited parts of the circuit and the unrequited external pins increases the package cost. Further, the energy (hereinafter called the running cost) consumed in the LSI during the operation unnecessarily shortens the battery life. Equation (1) takes only the chip manufacturing cost into account. This cost, however, fails to cover the entire actual cost and is required to include the running cost. Let E be the total of the package cost and the running cost. The chip unit cost is redefined as equation (5).
P=(D+M)/N+F+Exe2x80x83xe2x80x83(5)
An architecture of the system LSI is crucial for minimizing E and maximizing the reduction of the first term due to the mass production. For the conventional system LSI, however, there has been no manufacturing method conceived and realized from such a point of view.
The object of the present invention is to realize a method of manufacturing a system LSI which is not accompanied by an increased power consumption or increased running cost even in the case of reuse hardware and software for reducing the manufacturing cost.
In order to achieve the above-mentioned object, according to the present invention, there is provided a method of manufacturing a system LSI comprising the steps of determining the working area required of the memory and the processor from the datapath width required for activating an application program thereby to prevent power from being supplied to the unused area, thereby reusing and commonly using the hardware and software without increasing the running cost such as the power consumption.
Specifically, according to the invention, there is provided a method of manufacturing a system LSI having at least a processor and a memory in a single chip, comprising the steps of preparing a system LSI in the stage where a preset common process has been completed, determining the working area for activation of an application program mounted on the system LSI based on the datapath width of the processor and the datapath width and the number of words of the memory used upon activation of the application program, and completing the manufacture of the system LSI in such a manner as not to supply power to areas other than the working area.
FIGS. 1A and 2B are diagrams showing the difference between the conventional method of manufacturing the microcomputer and a method according to the invention. FIG. 1A shows the prior art, and FIG. 1B shows the invention.
As described above, in the conventional method of manufacturing the system LSI, the hardware is not customized but the range of reuse of the hardware is selectable while the software is customized. According to the method of manufacturing the system LSI of the present invention, in contrast, both the software and the hardware are customized, and the software design parameters are reflected in the hardware manufacturing process so that the LSI design data and mask data are reused. According to this invention, the unrequired power consumption of the system LSI is suppressed by several masks in the final design step to reduce the cost. The datapath width and the number of words in the memory are optimized in accordance with each application, and power is supplied only to the required parts to minimize the power consumption.
FIG. 2 is a diagram showing a general configuration for a method of manufacturing the system LSI according to this invention.
The LSI manufactured by this method is a system LSI with a core processor, a data memory, an instruction memory and peripheral circuits integrated in a single chip. In the method of manufacturing this system LSI, a general-purpose LSI chip 1 provides a base, and in accordance with the application program 2, the datapath width can be changed to an arbitrary length not more than the upper-limit datapath width of the general-purpose LSI chip 1. In addition, the datapath width of the core processor, the data memory and the instruction memory (also the peripheral circuit as required) is shortened so that power is not supplied to the areas not used, nor to the areas of the data memory and the instruction memory (and peripheral circuits as required) not used for execution of the application program 2, thus saving the unrequired power consumption.
Assume, for example, that the datapath width of the general-purpose LSI chip 1 is 64 bits and both the data memory and the instruction memory have a sufficient capacity. In designing a high-performance system LSI, a LSI 3-1 with the datapath width of 60 bits is employed, while in designing the system LSI of low power consumption, a LSI 3-4 with the datapath width of 7 bits is employed, while a 32-bit LSI 3-2 or a 20-bit LSI 3-3 is employed for the intermediate system. In this way, an LSI of an arbitrary datapath width can be employed. In other words, system LSIs having various datapath width can be designed from one general-purpose LSI. In addition, since a general-purpose LSI chip providing the base is customized in a stage near to the final step, the value N in the first term of equation (5) can become very large.
B. Shackleford, et al. report in xe2x80x9cEmbedded System Cost Optimization via Data path Width Adjustmentxe2x80x9d, IEICE Trans. Information and systems, Vol. E80-D, No. 10. pp. 974-981, October 1997, that the datapath width has a strong effect on the area and performance of the system. In xe2x80x9cA Programming Language for Processor-Based Embedded Systemsxe2x80x9d in Proc. of Fifth Asian Pacific Conf. on Hardware Description Languages, pp. 89-94, 1998, on the other hand, A. Inoue et al. report that the datapath width has a strong effect also on the power consumption.
By shortening the datapath width and thus saving the power supply to the areas not used, a LSI can be produced having the same power consumption as the LSI designed with the particular shortened datapath width. In the case where a general-purpose LSI chip having a 64-bit processor mounted thereon is designed and power supply to the most significant 16 bits is cut off in the manufacturing process, for example, it is possible to produce a system LSI operating in a similar manner to the system LSI having a 48-bit processor mounted thereon. In this way, the present invention can minimize the running cost.
Further, the package cost can also be minimized by disconnecting the electrode pads of the unused areas with external pins when packaging the system LSI. As described above, the method of manufacturing the system LSI according to this invention is expected to reduce both the first and third terms of equation (5).
An application program is described in a software language by which the system designer can set the variable length arbitrarily.
In the step of determining the working area, an application program is compiled using a compiler corresponding to the datapath width set by the system designer, and the program thus compiled is used for simulation.
As described above, the method of manufacturing the system LSI according to the invention can change the power consumption according to applications, and therefore one general-purpose LSI chip is applicable to broad fields (various application programs). As a result, one type of LSI can be mass produced, and the resulting increased production volume (with an increased N in equation (5)) can reduce the chip unit cost.
Also, the driving conditions of the processor, the data bus, the register and the bus can be designated in bits. By appropriately selecting the datapath width of the processor according to applications, therefore, the unrequired power consumption can be eliminated. The memory can be similarly reduced in power consumption, thereby leading to a lower package cost.
Further, the system LSI according to the invention, unlike the conventional LSI constituting a part, is a system itself. At the time of system design, therefore, the LSI is specialized simply by the development of software and customization in the last step of manufacture. The step of collecting the component parts of the system and integrating them inone chip is eliminated, and therefore the intended LSI can be designed in a short time.
Furthermore, in view of the fact that the system LSI is customized immediately before packaging, the unrequired pins are not included in the packaging process, thereby reducing the packaging cost.
In addition, the reuse of the LSI itself permits a high-accuracy estimation. Since the physical information of the LSI such as the wiring resistance is fixed, the estimation accuracy of the power consumption in the early design steps is improved. The high-accuracy estimation technique is crucial for determining the design parameters of the system LSI.